Semiconductor device and method of manufacturing the same

ABSTRACT

An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area. In this manner, the integration of a semiconductor device can be improved and an area occupied by the semiconductor device can be decreased without causing degradation of junction voltage resistance and increase of a junction leakage current in the semiconductor device.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device includingtransistors and connection between the transistors for constituting anLSI with high integration and a decreased area.

With the recent development of a semiconductor device with highintegration and high performance, there are increasing demands for morerefinement of the semiconductor device. The improvement of theconventional techniques cannot follow these demands, and noveltechniques are unavoidably introduced in some technical fields. Forexample, as a method of forming an isolation, the LOCOS isolation methodis conventionally adopted in view of its simpleness and low cost.Recently, however, it is considered that a trench buried type isolation(hereinafter referred to as the trench isolation) is more advantageousfor manufacturing a refined semiconductor device.

Specifically, in the LOCOS isolation method, since selective oxidationis conducted, the so-called bird's beak occurs in the boundary with amask for preventing the oxidation. As a result, the dimension of atransistor is changed because an insulating film of the isolationinvades a transistor region against the actually designed maskdimension. This dimensional change is unallowable in the refinement of asemiconductor device after the 0.5 μm generation. Therefore, even in themass-production techniques, the isolation forming method has started tobe changed to the trench isolation method in which the dimensionalchange is very small. For example, IBM corporation has introduced thetrench isolation structure as a 0.5 μm CMOS process for themass-production of an MPU (IBM Journal of Research and Development, VOL.39, No. 1/2, 1995, pp. 33-42).

Furthermore, in a semiconductor device mounting elements such as aMOSFET in an active area surrounded with an isolation, an insulatingfilm is deposited on the active area, the isolation and a gateelectrode, and a contact hole is formed by partly exposing theinsulating film for connection between the active area and aninterconnection member on a layer above the insulating film. Thisstructure is known as a very common structure for the semiconductordevice.

FIG. 17 is a sectional view for showing the structure of a conventionalsemiconductor device. In FIG. 17, a reference numeral 1 denotes asilicon substrate, a reference numeral 2 b denotes an isolation with atrench isolation structure which is made of a silicon oxide film andwhose top surface is flattened so as to be at the same level as the topsurface of the silicon substrate 1, a reference numeral 3 denotes a gateoxide film made of a silicon oxide film, a reference numeral 4 a denotesa polysilicon electrode working as a gate electrode, a reference numeral4 b denotes a polysilicon interconnection formed simultaneously with thepolysilicon electrode 4 a, a reference numeral 6 denotes alow-concentration source/drain region formed by doping the siliconsubstrate with an n-type impurity at a low concentration, a referencenumeral 7 a denotes an electrode sidewall, a reference numeral 7 bdenotes an interconnection sidewall, a reference numeral 8 denotes ahigh-concentration source/drain region formed by doping the siliconsubstrate with an n-type impurity at a high concentration, a referencenumeral 12 denotes an insulating film made of a silicon oxide film, anda reference numeral 13 denotes a local interconnection made of apolysilicon film formed on the insulating film 12.

The local interconnection 13 is also filled within a connection hole 14formed in a part of the insulating film 12, so as to be contacted withthe source/drain region in the active area through the connection hole14. In this case, the connection hole 14 is formed apart from theisolation 2 b by a predetermined distance. In other words, in theconventional layout rule for such a semiconductor device, there is arule that the edge of a connection hole is previously located away fromthe boundary between the active area and the isolation region so as toprevent a part of the connection hole 14 from stretching over theisolation 2 b even when a mask alignment shift is caused inphotolithography (this distance between the connection hole and theisolation is designated as an alignment margin).

However, in the structure of the semiconductor device as shown in FIG.17, there arise problems in the attempts to further improve theintegration for the following reason:

A distance La between the polysilicon electrode 4 a and the isolation 2b is estimated as an index of the integration. In order to prevent theconnection hole 14 from interfering the isolation 2 b as describedabove, the distance La is required to be 1.2 μm, namely, the sum of thediameter of the connection hole 14, that is, 0.5 μm, the width of theelectrode sidewall 7 a, that is, 0.1 μm, the alignment margin from thepolysilicon electrode 4 a, that is, 0.3 μm, and the alignment marginfrom the isolation 2 b, that is, 0.3 μm. A connection hole has attaineda more and more refined diameter with the development of processingtechniques, and also a gate length has been decreased as small as 0.3 μmor less. Still, the alignment margin in consideration of the maskalignment shift in the photolithography is required to be approximately0.3 μm. Accordingly, as the gate length and the connection hole diameterare more refined, the proportion of the alignment margin is increased.This alignment margin has become an obstacle to the high integration.

Therefore, attempts have been made to form the connection hole 14without considering the alignment margin in view of the alignment shiftin the photolithography. Manufacturing procedures adopted in such a casewill now be described by exemplifying an n-channel MOSFET referring toFIGS. 18(a) through 18(c).

First, as is shown in FIG. 18(a), after forming an isolation 2 b havingthe trench structure in a silicon substrate 1 doped with a p-typeimpurity (or p-type well), etch back or the like is conducted forflattening so as to place the surfaces of the isolation 2 b and thesilicon substrate 1 at the same level. In an active area surrounded withthe isolation 2 b, a gate oxide film 3, a polysilicon electrode 4 aserving as a gate electrode, an electrode sidewall 7 a, alow-concentration source/drain region 6 and a high-concentrationsource/drain region 8 are formed. On the isolation 2 b are disposed apolysilicon interconnection 4 b formed simultaneously with thepolysilicon electrode 4 a and an interconnection sidewall 7 b. At thispoint, the top surface of the high-concentration is source/drain region8 in the active area is placed at the same level as the top surface ofthe isolation 2 b. Then, an insulating film 12 of a silicon oxide filmis formed on the entire top surface of the substrate.

Next, as is shown in FIG. 18(b), a resist film 25 a used as a mask forforming a connection hole is formed on the insulating film 12, and theconnection hole 14 is formed by, for example, dry etching.

Then, as is shown in FIG. 18(c), the resist film 25 a is removed, and apolysilicon film is deposited on the insulating film 12 and within theconnection hole 14. The polysilicon film is then made into a desiredpattern, thereby forming a local interconnection 13.

At this point, in the case where the alignment margin in view of themask alignment shift in the formation of the connection hole 14 is notconsidered in estimating the distance La between the polysiliconelectrode 4 a and the isolation 2 b, a part of the isolation 2 b isincluded in the connection hole 14 when the exposing area of the resistfilm 25 a is shifted toward the isolation 2 b due to the mask alignmentshift in the photolithography. Through over-etch in conducting the dryetching of the insulating film 12, although the high-concentrationsource/drain region 8 made of the silicon substrate is not largelyetched because of its small etching rate, the part of the isolation 2 bincluded in the connection hole 14 is selectively removed, resulting informing a recess 40 in part of the connection hole 14. When the recess40 in the connection hole 14 has a depth exceeding a given proportion tothe depth of the high-concentration source/drain region 8, junctionvoltage resistance can be decreased and a junction leakage current canbe increased because the concentration of the impurity in thehigh-concentration source/drain region 8 is low at that depth.

In order to prevent these phenomena, it is necessary to provide apredetermined alignment margin as is shown in the structure of FIG. 17so as to prevent the connection hole 14 from interfering the isolation 2b even when the alignment shift is caused in the lithography. In thismanner, in the conventional layout rule for a semiconductor device, analignment margin in view of the mask alignment shift in thephotolithography is unavoidably provided.

Furthermore, a distance between the polysilicon electrode 4 a and theconnection hole 14 is also required to be provided with an alignmentmargin. Otherwise, the connection hole 14 can interfere the polysiliconelectrode 4 a due to the fluctuation caused in the manufacturingprocedures, resulting in causing electric short-circuit between an upperlayer interconnection buried in the connection hole and the gateelectrode.

As described above, it is necessary to provide the connection hole 14with margins for preventing the interference with other elements aroundthe connection hole, which has become a large obstacle to the highintegration of an LSI.

Also in the case where a semiconductor device having the so-calledsalicide structure is manufactured, the following problems are causeddue to a recess formed in the isolation:

FIG. 19 is a sectional view for showing an example of a semiconductordevice including the conventional trench isolation and a MOSFET havingthe salicide structure. As is shown in FIG. 19, a trench isolation 105 ais formed in a silicon substrate 101. In an active area surrounded withthe isolation 105 a, a gate insulating film 103 a, a gate electrode 107a, and electrode sidewalls 108 a on both side surfaces of the gateelectrode 107 a are formed. Also in the active area, a low-concentrationsource/drain region 106 a and a high-concentration source/drain region106 b are formed on both sides of the gate electrode 107 a. A channelstop region 115 is formed below the isolation 105 a. Furthermore, inareas of the silicon substrate 101 excluding the isolation 105 a and theactive area, a gate interconnection 107 b made of the same polysiliconfilm as that for the gate electrode 107 a is formed with a gateinsulating film 103 b sandwiched, and the gate interconnection 107 b isprovided with interconnection sidewalls 108 b on its both side surfaces.On the gate electrode 107 a, the gate interconnection 107 b and thehigh-concentration source/drain region 106 b, an upper gate electrode109 a, an upper gate interconnection 109 b and a source/drain electrode109 c each made of silicide are respectively formed. Furthermore, thissemiconductor device includes an interlayer insulating film 111 made ofa silicon oxide film, a metallic interconnection 112 formed on theinterlayer insulating film 111, and a contact member 113 (buriedconductive layer) filled in a connection hole formed in the interlayerinsulating film 111 for connecting the metallic interconnection 112 withthe source/drain electrode 109 c.

Now, the manufacturing procedures for the semiconductor device includingthe conventional trench isolation and the MOSFET with the salicidestructure shown in FIG. 19 will be described referring to FIGS. 20(a)through 20(e).

First, as is shown in FIG. 20(a), a silicon oxide film 116 and a siliconnitride film 117 are successively deposited on a silicon substrate 101,and a resist film 120 for exposing an isolation region and masking atransistor region is formed on the silicon nitride film 117. Then, byusing the resist film 120 as a mask, etching is conducted, so as toselectively remove the silicon nitride film 116 and the silicon oxidefilm 117, and further etch the silicon substrate 101, thereby forming atrench 104. Then, impurity ions are injected into the bottom of thetrench 104, thereby forming a channel stop region 115.

Then, as is shown in FIG. 20(b), a silicon oxide film (not shown) isdeposited, and the entire top surface is flattened until the surface ofthe silicon nitride film 117 is exposed. Through this procedure, atrench isolation 105 a made of the silicon oxide film filled in thetrench 104 is formed in the isolation region Reiso.

Next, as is shown in FIG. 20(c), after the silicon nitride film 117 andthe silicon oxide film 116 are removed, a gate oxide film 103 is formedon the silicon substrate 101, and a polysilicon film 107 is depositedthereon. Then, a photoresist film 121 for exposing areas excluding aregion for forming a gate is formed on the polysilicon film 107.

Then, as is shown in FIG. 20(d), by using the photoresist film 121 as amask, dry etching is conducted, thereby selectively removing thepolysilicon film 107 and the gate oxide film 103. Thus, a gate electrode107 a of the MOSFET in the transistor region Refet and a gateinterconnection 107 b stretching over the isolation 105 a and thesilicon substrate 101 are formed. After removing the photoresist film121, impurity ions are injected into the silicon substrate 101 by usingthe gate electrode 107 a as a mask, thereby forming a low-concentrationsource/drain region 106 a. Then, a silicon oxide film 108 is depositedon the entire top surface of the substrate.

Next, as is shown in FIG. 20(e), the silicon oxide film 108 isanisotropically dry-etched, thereby forming electrode sidewalls 108 aand interconnection sidewalls 108 b on both side surfaces of the gateelectrode 107 a and the gate interconnection 107 b, respectively. Atthis point, the gate oxide film 103 below the silicon oxide film 108 issimultaneously removed, and the gate oxide film 103 below the gateelectrode 107 a alone remains. Then, impurity ions are diagonallyinjected by using the gate electrode 107 a and the electrode sidewalls108 a as masks, thereby forming a high-concentration source/drain region106 b. Then, after a Ti film is deposited on the entire top surface,high temperature annealing is conducted, thereby causing a reactionbetween the Ti film and the components made of silicon directly incontact with the Ti film. Thus, an upper gate electrode 109 a, an uppergate interconnection 109 b and a source/drain electrode 109 c made ofsilicide are formed.

The procedures to be conducted thereafter are omitted, but thesemiconductor device including the MOSFET having the structure as shownin FIG. 19 can be ultimately manufactured. In FIG. 19, the metallicinterconnection 112 is formed on the interlayer insulating film 111, andthe metallic interconnection 112 is connected with the source/drainelectrode 109 c through the contact member 113 including a W plug andthe like filled in the contact hole.

When the aforementioned trench isolation structure is adopted, thedimensional change of the source/drain region can be suppressed becausethe bird's beak, that is, the oxide film invasion of an active area,which is caused in the LOCOS method where a thick silicon oxide film isformed by thermal oxidation, can be avoided. Furthermore, in theprocedure shown in FIG. 20(c), the surfaces of the isolation 105 a andthe silicon substrate 101 in the transistor region Refet are placed atthe same level.

In such a semiconductor device having the trench type isolation,however, there arise the following problems:

When the procedures proceed from the state shown in FIG. 20(d) to thestate shown in FIG. 20(e), the silicon oxide film 108 is anisotropicallyetched so as to form the sidewalls 108 a and 108 b. At this point,over-etch is required. Through this over-etch, the surface of theisolation 105 a is removed by some depth.

FIGS. 21(a) and 21(b) are enlarged sectional views around the boundarybetween the high-concentration source/drain region 106 b and theisolation 105 a after this over-etch.

As is shown in FIG. 21(a), between the procedures shown in FIGS. 20(d)and 20(e), the impurity ions are diagonally injected so as to form thehigh-concentration source/drain region 106 b. Through this ioninjection, the high-concentration source/drain region 106 b is formedalso below the edge of the isolation 105 a because the isolation 105 ais previously etched by some depth. Accordingly, the high-concentrationsource/drain region 106 b is brought closer to the channel stop region115, resulting in causing the problems of degradation of the junctionvoltage resistance and increase of the junction leakage current.

In addition, as is shown in FIG. 21(b), in the case where the Ti film orthe like is deposited on the high-concentration source/drain region 106b so as to obtain the silicide layer through the reaction with thesilicon below, the thus formed silicide layer can invade the interfacebetween the silicon substrate 101 and the isolation 105 a with ease. Asa result, a short-circuit current can be caused between the source/drainelectrode 109 c made of silicide and the channel stop region 115.

SUMMARY OF THE INVENTION

The object of the present invention is improving the structure of anisolation, so as to prevent the problems caused because the edge of theisolation is trenched in etching for the formation of a connection holeor sidewalls.

In order to achieve the object, the invention proposes first and secondsemiconductor devices and first through third methods of manufacturing asemiconductor device as described below.

The first semiconductor device of this invention in which asemiconductor element is disposed in each of plural active areas in asemiconductor substrate comprises an isolation for surrounding andisolating each active area, the isolation having a top surface at ahigher level than a surface of the active area and having a step portionin a boundary with the active area; an insulating film formed so as tostretch over each active area and the isolation; plural holes eachformed by removing a portion of the insulating film disposed at least onthe active area; plural buried conductive layers filled in therespective holes; and plural interconnection members formed on theinsulating film so as to be connected with the respective active areasthrough the respective buried conductive layers.

Owing to this structure, in the case where a part of or all the holesare formed so as to stretch over the active areas and the isolation dueto mask alignment shift in photolithography, a part of the isolation isremoved by over-etch for ensuring the formation of the holes. In such acase, even when the top surface of the isolation is trenched to be lowerthan the surface of the active area, the depth of the holes formed inthe isolation is small in the boundary with the active area because ofthe level difference between the top surface of the isolation and thesurface of the active area. Accordingly, degradation of the junctionvoltage resistance and increase of the junction leakage current can besuppressed. Therefore, there is no need to provide a portion of theactive area where each hole is formed with an alignment margin foravoiding the interference with the isolation caused by the maskalignment shift in the lithography. Thus, the area of the active areacan be decreased, resulting in improving the integration of thesemiconductor device.

In the first semiconductor device, at least a part of the plural holescan be formed so as to stretch over the active area and the isolationdue to fluctuation in manufacturing procedures.

In other words, even when no margin for the mask alignment in thelithography is provided, the problems caused in the formation of theholes can be avoided.

Furthermore, the angle between a side surface of the step portion andthe surface of the active area is preferably 70 degrees or more.

As a result, when the hole interferes the isolation, the part of theisolation included in the hole is definitely prevented from being etchedthrough over-etch in the formation of the holes down to a depth wherethe impurity concentration is low in the active area.

The isolation is preferably a trench isolation made of an insulatingmaterial filled in a trench formed by trenching the semiconductorsubstrate by a predetermined depth.

This is because no bird's beak is caused in the trench isolationdifferently from a LOCOS film as described above, and hence, the trenchisolation is suitable particularly for the high integration andrefinement of the semiconductor device.

In the first semiconductor device, when the semiconductor element is aMISFET including a gate insulating film and a gate electrode formed onthe active area; and source/drain regions formed in the active area onboth sides of the gate electrode, the following preferred embodimentscan be adopted:

The semiconductor device can further comprise a gate interconnectionmade of the same material as that for the gate electrode and formed onthe isolation, each of the holes can be formed on an area including thesource/drain region, the isolation and the gate interconnection, and theplural interconnection members can be connected with the gateinterconnection on the isolation.

Owing to this configuration, in the case where the interconnectionmembers work as local interconnections for connecting a gateinterconnection on the isolation with the active area, there is no needto separately form holes in the insulating film on the gateinterconnection and the insulating film on the active area. In addition,there is no need to provide the separate holes with alignment marginsfrom the boundary between the active area and the isolation.Accordingly, the area of the isolation can also be decreased, resultingin largely improving the integration of the semiconductor device.

The semiconductor device can further comprise electrode sidewalls madeof an insulating material and formed on both side surfaces of the gateelectrode; and a step sidewall made of the same material as theinsulating material for the electrode sidewalls and formed on the sidesurface of the step portion. In this semiconductor device, at least apart of the holes can be formed by also removing a portion of theinsulating film disposed on the step sidewall.

Owing to this structure, the abrupt level difference between thesurfaces of the isolation and the active area can be released by thestep sidewall. Therefore, a residue is scarcely generated in patterningthe interconnection members, and an upper interconnection is preventedfrom being disconnected and increasing in its resistance.

The semiconductor device can further comprise a gate protection filmformed on the gate electrode, and at least a part of the holes can beformed so as to stretch over the source/drain region and at least a partof the gate protection film.

Owing to this structure, a part of the gate protection film included inthe hole is removed by the over-etch in the formation of the holes.However, the gate electrode is protected by the gate protection film,and hence, electrical short circuit between the gate electrode and theinterconnection member can be prevented. Accordingly, there is no needto provide an alignment margin from the gate electrode in the area whereeach hole is formed, resulting in further improving the integration.

The interconnection members can be first layer metallicinterconnections, and the insulating film can be an interlayerinsulating film disposed between the semiconductor substrate, and thefirst layer metallic interconnections. In this case, the semiconductordevice preferably further comprises, between the interlayer insulatingfilm and the semiconductor substrate an underlying film made of aninsulating material having high etching selectivity against theinterlayer insulating film.

The second semiconductor device of this invention in which asemiconductor element is disposed in each of plural active areas in asemiconductor substrate comprises a trench isolation for isolating andsurrounding each active area, the trench isolation having a top surfaceat a higher level than a surface of the active area and having a stepportion in a boundary with the active area; and a step sidewall formedon the side surface of the step portion of the trench isolation.

Owing to this structure, in the impurity ion injection for the formationof an impurity diffused layer of the semiconductor device, the stepsidewall disposed at the edge of the trench isolation can prevent theimpurity ions from being implanted below the edge of the isolation.Furthermore, also in adopting the structure including a source/drainelectrode made of silicide, the step sidewall can prevent the silicidelayer from being formed at a deep portion. Therefore, a short circuitcurrent can be prevented from occurring between the source/drainelectrode and a substrate region such as the channel stop region. Inthis manner, the function of the trench isolation to isolate eachsemiconductor element can be prevented from degrading.

In the second semiconductor device, the step sidewall is preferably madeof an insulating material.

Also in the second semiconductor device, the semiconductor element canbe a MISFET including a gate insulating film and a gate electrode formedon the active area; and source/drain regions formed in the active areaon both sides of the gate electrode. This semiconductor device can befurther provided with electrode sidewalls formed on both side surfacesof the gate electrode, and the step sidewall can be formedsimultaneously with the electrode sidewalls.

Owing to this structure, the semiconductor elements can be a MISFEThaving the LDD structure suitable for the refinement. Because of thisstructure together with the trench isolation structure, thesemiconductor device can attain a structure particularly suitable forthe refinement and the high integration.

The first method of manufacturing a semiconductor device in which asemiconductor element is disposed in each of plural active areas in asemiconductor substrate comprises a first step of forming an isolationin a part of the semiconductor substrate, the isolation having a topsurface at a higher level than a surface of the semiconductor substrateand having a step portion in a boundary with the surface of thesemiconductor substrate; a second step of introducing an impurity at ahigh concentration into each active area of the semiconductor substratesurrounded by the isolation; a third step of forming an insulating filmon the active area and the isolation; a fourth step of forming, on theinsulating film, a masking member having an exposing area above an areaat least including a portion of the active area where the impurity atthe high concentration is introduced; a fifth step of conducting etchingby using the masking member so as to selectively remove the insulatingfilm and form holes; and a sixth step of forming a buried conductivelayer by filling the holes with a conductive material and forming, onthe insulating film, interconnection members to be connected with theburied conductive layer. In this method, in the fourth step, analignment margin is not provided for preventing the exposing area of themasking member from including a portion above the isolation when maskshift is caused in photolithography.

In adopting this method, even when a part of the isolation is removed byover-etch in the fifth step so that the top surface of the isolation isetched to be lower than the surface of the active area, the depth of theholes formed in the isolation is small because of the level differencebetween the isolation and the active area. Accordingly, the decrease ofthe junction voltage resistance and the increase of the junction leakagecurrent can be suppressed in the manufactured semiconductor device. Inaddition, the area of the active area can be decreased because noalignment margin from the isolation is provided, resulting in improvingthe integration of the manufactured semiconductor device.

In the first method of manufacturing a semiconductor device, thefollowing preferred embodiments can be adopted:

The fifth step is preferably performed so as to satisfy the followinginequality:OE×a×(ER 2/ER 1)≦b+D×(2/10)wherein “a” indicates a thickness of the insulating film, “b” indicatesa level difference between the surface of the active area and the topsurface of the isolation, “ER1” indicates an etching rate of theinsulating film, “ER2” indicates an etching rate of the isolation, “D”indicates a depth of an impurity diffused layer in the active area, and“OE” indicates an over-etch ratio of the insulating film.

In adopting this method, even when a part of the isolation included inthe hole is removed by over-etch in the formation of the holes, thebottom of the etched portion does not reach a portion where the impurityconcentration is low in the active area. In other words, the top surfaceof the isolation is never placed at a lower level than the surface ofthe active area. Accordingly, the degradation of the junction voltageresistance and the increase of the junction leakage current can bedefinitely prevented in the manufactured semiconductor device.

When the semiconductor element is a MISFET, the method can furtherinclude, before the second step, a step of forming a gate insulatingfilm on the active area, a step of depositing a conductive film on thegate insulating film and a step of forming a gate electrode bypatterning the conducive film, and in the second step, the impurity atthe high concentration is introduced so as to form a source/drainregion. In such a case, the following preferred embodiments can beadopted.

The method can further comprise, after the step of depositing theconductive film, a step of depositing a protection insulating film onthe conductive film, and in the step of forming the gate electrode, theconductive film as well as the protection insulating film are patterned,so as to form a gate protection film on the gate electrode. The fifthstep can be performed so as to satisfy the following inequality:OE×a×(ER 3/ER 1)<cwherein “a” indicates a thickness of the insulating film, “c” indicatesa thickness of the gate protection film, “ER1” indicates an etching rateof the insulating film, “ER3” indicates an etching rate of the gateprotection film and “OE” indicates an over-etch ratio of the insulatingfilm.

When this method is adopted, while the area of the active area isdecreased by not providing an alignment margin for avoiding theinterference between the connection hole and the gate electrode, thehole is prevented from reaching the gate electrode below the gateprotection film.

In the fourth step, the masking member can be formed to be positionedwithout providing a margin for preventing the exposing area thereof fromincluding a portion above the gate protection film even when the maskshift is caused in the photolithography.

Alternatively, in the fourth step, the masking member can be formed tobe positioned with the exposing area thereof including at least a partof a portion above the gate protection film when the mask shift is notcaused in the photolithography.

In the third step, an interlayer insulating film can be formed as theinsulating film, and in the sixth step, first layer metallicinterconnections can be formed as the interconnection members. In such acase, it is preferred that the interlayer insulating film is formed inthe third step after an underlying film made of an insulating materialhaving high etching selectivity against the interlayer insulating filmis formed below the interlayer insulating film.

The second method of manufacturing a semiconductor device of thisinvention comprises a first step of forming an underlying insulatingfilm on a semiconductor substrate; a second step of depositing anetching stopper film on the underlying insulating film; a third step offorming a trench by exposing a portion of the etching stopper film andthe underlying insulating film where an isolation is to be formed andetching the semiconductor substrate in the exposed portion; 5 a fourthstep of depositing an insulating film for isolation on an entire topsurface of the substrate, flattening the substrate until at least asurface of the etching stopper film is exposed, and forming a trenchisolation in the trench so as to surround a transistor region; a fifthstep of removing, by etching, at least the etching stopper film and theunderlying insulating film, so as to expose a step portion between thetransistor region and the trench isolation; a sixth step of depositing agate oxide film and a conductive film on the substrate and making theconductive film into a pattern of at least a gate electrode; a seventhstep of depositing an insulating film for sidewalls on the entire topsurface of the substrate and anisotropically etching the insulating filmfor the sidewalls, so as to form electrode sidewalls and a step sidewallon side surfaces of the gate electrode and the step portion,respectively; and an eighth step of introducing an impurity into thesemiconductor substrate in the transistor region on both sides of thegate electrode, so as to form source/drain regions.

When this method is adopted, since the step sidewall is formed betweenthe semiconductor substrate in the transistor region and the trenchisolation after completing the fifth step, the impurity ions areprevented from being implanted below the edge of the trench isolation inthe impurity ion injection in the eighth step. Furthermore, also when anarea in the vicinity of the surface of the source/drain region issubsequently silicified, the step sidewall made of the insulating filmcan prevent the silicide layer from being formed at a deep portion.Accordingly, not only the degradation of the junction voltage resistanceand the current leakage but also the occurrence of a short circuitcurrent between the source/drain electrode and the substrate region suchas the channel stop region can be prevented.

In the second method of manufacturing a semiconductor device, thefollowing preferred embodiments can be adopted:

In the second step, the thickness of the etching stopper film ispreferably determined in consideration of an amount of over-etch in theseventh step, so that the step portion having a level difference with apredetermined size or more is exposed in the fifth step.

The method can further comprise, after completing the eighth step, astep of silicifying at least an area in the vicinity of the surface ofthe source/drain region.

The third method of manufacturing a semiconductor device of thisinvention comprises a first step of forming a gate insulating film on asemiconductor substrate; a second step of depositing a first conductivefilm to be formed into a gate electrode on the gate insulating film; athird step of forming a trench by exposing a portion of the firstconductive film where a trench isolation is to be formed and etching thesemiconductor substrate in the exposed portion; a fourth step ofdepositing an insulating film for isolation on an entire top surface ofthe substrate, flattening the substrate at least until a surface of thefirst conductive film is exposed, and forming the trench isolation inthe trench so as to surround a transistor region; a fifth step ofdepositing a second conductive film to be formed into at least an uppergate electrode on the entire top surface of the flattened substrate; asixth step of making the first and second conductive films into apattern at least of the gate electrode and exposing a step portionbetween the transistor region and the trench isolation; a seventh stepof depositing an insulating film for sidewalls on the entire top surfaceof the substrate and anisotropically etching the insulating film for thesidewalls, so as to form electrode sidewalls and a step sidewall on sidesurfaces of the gate electrode and the step portion, respectively; andan eighth step of introducing an impurity into the semiconductorsubstrate in the transistor region on both sides of the gate electrode,so as to form source/drain regions.

When this method is adopted, the same effects as those attained by thesecond method of manufacturing a semiconductor device can be attained.In addition, in the patterning process for the gate electrode, the topsurface of the substrate is completely flat, and hence, the patterningaccuracy for the gate electrode can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1(a) through 1(d) are sectional views for showing manufacturingprocedures of Embodiment 1 up to the formation of an isolation;

FIGS. 2(a) through 2(e) are sectional views for showing themanufacturing procedures of Embodiment 1 after the formation of theisolation;

FIGS. 3(a) through 3(f) are sectional views for showing manufacturingprocedures of Embodiment 2 after the formation of an isolation;

FIGS. 4(a) through 4(c) are sectional views for showing manufacturingprocedures of Embodiment 3;

FIGS. 5(a) through 5(c) are sectional views for showing manufacturingprocedures of Embodiment 4;

FIGS. 6(a) through 6(f) are sectional views for showing manufacturingprocedures of Embodiment 5;

FIGS. 7(a) through 7(c) are sectional views for showing manufacturingprocedures of Embodiment 6;

FIGS. 8(a) through 8(c) are sectional views for showing manufacturingprocedures of Embodiment 7 in which a comparatively thin insulating filmof Embodiment 1 is replaced with a layered film and an interlayerinsulating film;

FIGS. 9(a) through 9(c) are sectional views for showing themanufacturing procedures of Embodiment 7 in which a comparatively thininsulating film of Embodiment 2 is replaced with a layered film and aninterlayer insulating film;

FIGS. 10(a) through 10(c) are sectional views for showing themanufacturing procedures of Embodiment 7 in which a comparatively thininsulating film of Embodiment 4 is replaced with a layered film and aninterlayer insulating film;

FIGS. 11(a) through 11(c) are sectional views for showing themanufacturing procedures of Embodiment 7 in which a comparatively thininsulating film of Embodiment 5 is replaced with a layered film and aninterlayer insulating film;

FIG. 12 is a sectional view for showing the structure of a semiconductordevice of Embodiment 8;

FIGS. 13(a) through 13(e) are sectional views for showing manufacturingprocedures for the semiconductor device of Embodiment 8;

FIGS. 14(a) through 14(e) are sectional views for showing manufacturingprocedures for a semiconductor device of Embodiment 9;

FIGS. 15(a) through 15(f) are sectional views for showing manufacturingprocedures for a semiconductor device of Embodiment 10;

FIGS. 16(a) through 16(e) are sectional views for showing manufacturingprocedures for a semiconductor device of Embodiment 11;

FIG. 17 is a sectional view of a conventional semiconductor device inwhich the surfaces of an active area and a trench isolation are placedat the same level;

FIGS. 18(a) through 18(c) are sectional views for showing manufacturingprocedures for the conventional semiconductor device of FIG. 17;

FIG. 19 is a sectional view of a conventional semiconductor devicehaving a salicide structure and a trench isolation structure;

FIGS. 20(a) through 20(e) are sectional views for showing manufacturingprocedures for the conventional semiconductor device of FIG. 19; and

FIGS. 21(a) and 21(b) are partial sectional views for showing problems,in a conventional semiconductor device having a trench isolation,occurring in an impurity ion injection process and a silicifyingprocess, respectively.

DETAILED DESCRIPTION OF THE INVENTION Embodiment 1

Embodiment 1 of the invention will now be described referring to FIGS.1(a) through 1(d) and 2(a) through 2(e). In the manufacturing proceduresof this embodiment, a connection hole for connecting an interconnectionlayer and a silicon substrate is designed to stretch over an active areaand an isolation when alignment shift is not caused in photolithography.

In this embodiment, the isolation is formed as a trench isolation.Furthermore, interconnection to be formed above is assumed to be localinterconnection in which an insulating film can be comparatively thin,but the embodiment is applicable also to general global interconnectionformed on a thick S interlayer insulating film.

First, as is shown in FIG. 1(a), a resist film 50a having apredetermined pattern is formed on a p-type silicon substrate 1 (or ap-type well). The silicon substrate 1 is dry-etched by using the resistfilm 50 a as a mask, thereby forming a trench 51 with a depth of 1 μm.

Then, as is shown in FIG. 1(b), the resist film 50 a is removed, andthen a silicon oxide film 2 x is deposited on the entire top surface ofthe silicon substrate 1. Through this procedure, the previously formedtrench 51 is filled with the silicon oxide film 2 x.

Next, as is shown in FIG. 1(c), the silicon oxide film 2 x on thesilicon substrate 1 is removed by, for example, a CMP (chemicalmechanical polishing) method or etch-back through dry etching using aresist film, and at the same time, a trench isolation 2 b is formed. Atthis point, the top surface of the silicon substrate 1 and the topsurface of the isolation 2 b are flattened with no level differencetherebetween.

Then, as is shown in FIG. 1(d), dry etching with high etch selectivityis conducted so as to etch the silicon substrate 1 alone by a thicknessof 0.2 μm. Thus, a step portion which is higher in a stepwise mannerthan the top surface of the silicon substrate 1 by 0.2 μm is formed inthe isolation 2 b. The level difference caused by the step portion isrequired to be sufficiently large in consideration of an amount ofover-etch in etching a subsequently formed insulating film 12, andhence, the level difference is preferably equal to or larger than thethickness of the insulating film 12.

It is noted that the method of causing the level difference between thetop surface of the isolation 2 b and the surface of the active area isnot limited to that described above. For example, the level differencecan be caused as follows: After an etching stopper film having athickness corresponding to the level difference is previously depositedon the silicon substrate, a trench is formed and an insulating film forthe trench isolation is deposited. Then, the entire top surface of thesubstrate is flattened by the CMP method or the like, and the etchingstopper film is subsequently removed.

Next, As is shown in FIG. 2(a), after forming a gate oxide film 3 on thesilicon substrate 1, a polysilicon film 4 x is deposited on the entiretop surface of the substrate.

Then, as is shown in FIG. 2(b), after forming a resist film (not shown)having a predetermined pattern on the polysilicon film 4 x, dry etchingis conducted so as to form a polysilicon electrode 4 a on the activearea and a polysilicon interconnection 4 b on the isolation 2 b. Then,by using the gate electrode 4 a as a mask, n-type impurity ions areinjected at a high concentration, thereby forming high-concentrationsource/drain regions 8 in the silicon substrate 1 on both sides of thepolysilicon electrode 4 a.

After this, as is shown in FIG. 2(c), the insulating film 12 having athickness of, for example, 0.15 μm is deposited, so that aninterconnection subsequently formed above the insulating film (i.e., thelocal interconnection in this embodiment) can be electrically insulatedfrom the polysilicon electrode, the polysilicon interconnection and theactive area.

Next, as is shown in FIG. 2(d), a resist film 25 a having a pattern forforming a connection hole is formed on the insulating film 12. At thispoint, the exposing area of the resist film 25 a is positioned withoutan alignment margin for preventing interference with the isolation 2 b.In this embodiment, after the resist film 25 a is formed so that theexposing area stretches over the source/drain region 8, that is, theactive area of a transistor, and the isolation 2 b, dry etching isconducted by using the resist film 25 a as a mask, thereby forming aconnection hole 14 by removing the insulating film 12 in the exposingarea of the resist film 25 a. At this point, when the insulating film 12is, for example, 40% over-etched than its thickness of 0.15 μm in orderto ensure the formation of the connection hole 14, the isolation 2 b inthe exposing area of the resist film 25 a is etched by a thickness ofapproximately 0.06 μm. However, in this embodiment, the step portion hasa height of 0.2 μm, which is sufficiently larger than this etchedamount, and hence, a recess where the top surface of the isolation 2 bis lower than the top surface of the silicon substrate 1 is never formedin any part of the connection hole 14.

Next, as is shown in FIG. 2(e), a polysilicon film is deposited on theentire top surface and is patterned, thereby forming the localinterconnection 13. At this point, the local interconnection 13 is alsoformed within the connection hole 14, so as to be electrically connectedwith the source/drain region 8 serving as the active area.

In a semiconductor device formed in the aforementioned procedures, thetop surface of the isolation 2 b is higher in a stepwise manner than thesurface of the active area. Therefore, even when the isolation 2 b isremoved by some amount by the over-etch in dry etching the insulatingfilm 12, the isolation 2 b is prevented from being etched by a thicknessexceeding the level difference caused by the step portion. Accordingly,when mask alignment is shifted in the photolithography, a recess with adepth reaching a certain depth of the source/drain region 8 is preventedfrom being formed in the connection hole 14. As a result, theconventional problems, that is, the degradation of the junction voltageresistance and the increase of the junction leakage current causedbecause of the low impurity concentration at a lower part of the activearea of the silicon substrate corresponding to the sidewall of therecess, can be effectively prevented.

However, the level difference between the top surface of the isolation 2b and the surface of the active area is not necessarily required to belarger than the thickness of the insulating film 12. The dimensions andmaterials of the respective components can be determined so as tosatisfy the following inequality (1), wherein “a” denotes the thicknessof the insulating film 12; “b” denotes the level difference between thetop surface of the isolation 2 b and the surface of the active area;“ER1” denotes the etching rate of the insulating film 12; “ER2” denotesthe etching rate of the isolation 2 b; “D” denotes the depth of animpurity diffused layer in the active area; and “OE” denotes theover-etch ratio of the insulating film 12 in the formation of theconnection hole 14.OE×a×(ER 2/ER 1)≦b+D×(2/10)   (1)As far as the inequality (1) is satisfied, even when a part of theisolation 2 b is removed to be at a lower level than the surface of thesilicon substrate in the active area through the formation of theconnection hole 14, so that the recess 40 as is shown in FIG. 18(c) isformed in a part of the connection hole 14, the bottom of the recess 40is prevented from reaching the depth where the impurity concentration islow.

Since the alignment margin in view of the mask shift in thephotolithography can be omitted, the following effects can be attained:When a distance Lb between the polysilicon electrode 4 a serving as thegate electrode and the isolation 2 b is estimated as an index of theintegration, the distance Lb is 0.8 μm, namely, the sum of the diameterof the connection hole, 0.5 μm, and the alignment margin from the gateelectrode, 0.3 μm. Thus, the distance Lb can be decreased by 0.4 m ascompared with the conventional distance La of 1.2 μm (shown in FIG. 17).

Embodiment 2

Embodiment 2 will now be described referring to FIGS. 3(a) through 3(f).In this embodiment, a connection hole for connecting an interconnectionlayer and a silicon substrate is formed so as to stretch over an activearea and an isolation in the same manner as in Embodiment 1, and a stepportion between the isolation and the active area is provided with asidewall.

First, as is shown in FIGS. 3(a) and 3(b), an isolation 2 b whose topsurface is higher in a stepwise manner than the surface of an activearea by a predetermined level difference and a gate oxide film 3 areformed on a silicon substrate 1 in the same manner as described inEmbodiment 1. Then, a polysilicon film 4 x is deposited on the entiretop surface.

Next, the polysilicon film 4 x is patterned, thereby forming apolysilicon electrode 4 a and a polysilicon interconnection 4 b. Theprocedures conducted so far are identical to those adopted inEmbodiment 1. Then, a silicon oxide film is deposited on the entire topsurface and is subjected to anisotropic etching, thereby formingelectrode sidewalls 7 a on both side surfaces of the polysiliconelectrode 4 a and interconnection sidewalls 7 b on both side surfaces ofthe polysilicon interconnection 4 b. At the same time, a step sidewall 7c is formed on the side surface of the step portion between theisolation 2 b and the active area. Each of the sidewalls has a width of,for example, approximately 0.1 μm. After forming the polysiliconelectrode 4 a, an n-type impurity with a low concentration ision-injected into the active area, so as to form a low-concentrationsource/drain region 6. After forming the electrode sidewalls 7 a, ann-type impurity with a high concentration is ion-injected into theactive area, so as to form a high-concentration source/drain region 8.This is a generally adopted method of manufacturing a MOSFET having theso-called LDD structure.

Then, as is shown in FIGS. 3(d) through 3(f), the procedures asdescribed in Embodiment 1 referring to FIGS. 2(c) through 2(e) areconducted, thereby forming an insulating film 12 and a localinterconnection 13 thereon.

This embodiment can achieve the effect to improve the integrationsimilarly to Embodiment 1. In addition, owing to the step sidewall 7 c,the abrupt level difference between the isolation 2 b and the activearea can be released. As a result, the amount of residue generated inthe formation of the local interconnection 13 by patterning thepolysilicon film can be advantageously decreased, and disconnection ofthe local interconnection 13 and resistance increase thereof can also beprevented.

At this point, a distance Lc between the polysilicon electrode 4 aserving as a gate electrode and the isolation 2 b is estimated as anindex of the integration. The distance Lc is 1.0 μm, namely, the sum ofthe diameter of the connection hole, 0.5 μm, the width of the electrodesidewall 7 a, 0.1 μm, the alignment margin from the polysiliconelectrode 4 a, 0.3 μm, and the width of the step sidewall 7 c, 0.1 μm.Thus, the distance Lc can be decreased by 0.2 μm as compared with theconventional distance La of 1.2 μm (shown in FIG. 17).

Embodiment 3

Embodiment 3 will now be described referring to FIGS. 4(a) through 4(c).

In manufacturing procedures described in this embodiment, a connectionhole is formed so as to stretch over an active area and an isolationonly when mask alignment shift is caused in the photolithography.

FIG. 4(a) shows a state where the procedures described in Embodiment 2referring to FIGS. 3(a) through 3(d) have been completed. Specifically,as is shown in FIG. 4(a), after an isolation 2 b with a top surfacehigher in a stepwise manner than the surface of an active area, a stepsidewall 7 c on the side surface of the step portion of the isolation 2b, a gate oxide film 3, a polysilicon electrode 4 a serving as a gateelectrode, electrode sidewalls 7 a on both side surfaces of thepolysilicon electrode 4 a, a low-concentration source/drain region 6, ahigh-concentration source/drain region 8, a polysilicon interconnection4 b on the isolation 2 b, and interconnection sidewalls 7 b on both sidesurfaces of the polysilicon interconnection 4 b are formed, aninsulating film 12 with a thickness of approximately 0.15 μm is formedon the entire top surface.

Next, as is shown in FIG. 4(b), a resist film 25 b for forming aconnection hole is formed. At this point, in this embodiment, the resistfilm 25 b is formed so that the connection hole stretches over theactive area (i.e., the high-concentration source/drain region 8) and thestep sidewall 7 c when the mask alignment shift is not caused in thelithography. Then, the insulating film 12 is etched, thereby forming theconnection hole 14 stretching over the active area and the step sidewall7 c.

Then, as is shown in FIG. 4(c), a local interconnection 13 to beconnected with the high-concentration source/drain region 8 is formed onthe insulating film 12.

In the state shown in FIG. 4(b), the edge of the connection hole 14 canbe shifted toward the isolation 2 b by a maximum of 0.3 μm due to themask alignment shift in the lithography. In such a case, the resultantstructure becomes that described in Embodiment 2 (shown in FIG. 3(e)).However, no recess is formed in the isolation 2 b within the connectionhole 14 as described in Embodiments 1 and 2 even in such a case.Alternatively, even if a recess is formed, the problems of thedegradation of the junction voltage resistance and the increase of thejunction leakage current can be avoided as far as the dimensions and thelike of the respective components are determined so as to satisfy theinequality (1).

Also in this embodiment, a distance Lc between the polysilicon electrode4 a and the isolation 2 b is estimated as an index of the integration.Similarly to Embodiment 2, the distance Lc is 1.0 μm, namely, the sum ofthe diameter of the connection hole, 0.5 μm, the width of the electrodesidewall 7 a, 0.1 μm, the alignment margin from the polysiliconelectrode 4 a, 0.3 μm, and the width of the step sidewall 7 c, 0.1 μm.Thus, the distance Lc can be decreased by 0.2 μm as compared with theconventional distance La of 1.2 μm.

Embodiment 4

Embodiment 4 will now be described referring to FIGS. 5(a) through 5(c).In manufacturing procedures described in this embodiment, a connectionhole for connecting an interconnection layer and a silicon substrate isformed so as to stretch over an active area and a polysiliconinterconnection on an isolation.

FIG. 5(a) shows the state where the procedures described in Embodiment 2referring to FIGS. 3(a) through 3(d) have been completed. Specifically,as is shown in FIG. 5(a), after an isolation 2 b with a top surfacehigher in a stepwise manner than the surface of the active area, a stepsidewall 7 c on the side surface of the step portion of the isolation 2b, a gate oxide film 3, a polysilicon electrode 4 a serving as a gateelectrode, electrode sidewalls 7 a on both side surfaces of thepolysilicon electrode 4 a, a low-concentration source/drain region 6, ahigh-concentration source/drain region 8, a polysilicon interconnection4 b on the isolation 2 b, and interconnection sidewalls 7 b on both sidesurfaces of the polysilicon interconnection 4 b are formed, aninsulating film 12 with a thickness of approximately 0.15 μm is formedon the entire top surface.

Next, as is shown in FIG. 5(b), a resist film 25 c for forming aconnection hole is formed. In this embodiment, the resist film 25 c isformed with its exposing area stretching over the active area (i.e., thehigh-concentration source/drain region 8) and the polysiliconinterconnection 4 b on the isolation 2 b when the mask alignment shiftis not caused in the lithography. Then, the insulating film 12 isetched, thereby forming the connection hole 14 stretching over thehigh-concentration source/drain region 8, the isolation 2 b and thepolysilicon interconnection 4 b.

Then, as is shown in FIG. 5(c), a local interconnection 13 to beconnected with the high-concentration source/drain region 8 and thepolysilicon interconnection 4 b is formed on the insulating film 12.

When the high-concentration source/drain region 8 is to be electricallyconnected with the polysilicon interconnection 4 b serving as a gateinterconnection formed on the isolation 2 b in the conventionalmanufacturing procedures, a connection hole formed on thehigh-concentration source/drain region 8 and another connection holeformed on the polysilicon interconnection 4 b are required to bepositioned in consideration of alignment margins from the boundarieswith the high-concentration source/drain region 8 and the isolation 2 b,respectively. In contrast, in this embodiment, the interconnectionmember can be connected with the high-concentration source/drain region8 and the polysilicon electrode 4 b through one connection hole 14without consideration of the alignment margins. In addition, asdescribed in Embodiments 1 through 3, the problems of the degradation ofthe junction voltage resistance and the increase of the junction leakagecurrent can be prevented from being caused through the over-etch inetching the insulating film 12.

In this embodiment, the interconnection on the isolation 2 b is made ofa polysilicon film, but another conductive material or aninterconnection on a layer different from the polysilicon electrode canbe used instead.

Embodiment 5

Embodiment 5 will now be described referring to FIGS. 6(a) through 6(f).In manufacturing procedures described in this embodiment, a connectionhole for connecting an interconnection layer and a silicon substrate isformed so as to stretch over an active area, a gate electrode and anisolation.

First, as is shown in FIG. 6(a), an isolation 2 b with a top surfacehigher in a stepwise manner than the surface of a p-type siliconsubstrate 1 is formed.

Next, as is shown in FIG. 6(b), a polysilicon film 4 x with a thicknessof 0.2 μm is deposited on the entire top surface, and a silicon oxidefilm 15 x for gate protection with a thickness of approximately 0.15 μmis deposited on the polysilicon film 4 x. At this point, the thicknessof the silicon oxide film 15 x for gate protection is required to besufficiently large in consideration of an amount of over-etch to beremoved in etching a subsequently formed insulating film 12. In thisembodiment, the thickness of the silicon oxide film 15 x issubstantially the same as that of the insulating film 12.

Then, as is shown in FIGS. 6(c) and 6(d), the procedures as described inEmbodiment 2 referring to FIGS. 3(c) and 3(d) are conducted. Thus, aftera polysilicon electrode 4 a and a gate protection film 15 a togetherserving as a gate electrode, electrode sidewalls 7 a on both sidesurfaces of the polysilicon electrode 4 a and the gate protection film15 a, a low-concentration source/drain region 6, a high-concentrationsource/drain region 8, a polysilicon interconnection 4 b and aninterconnection protection film 15 b on the isolation 2 b,interconnection sidewalls 7 b on both side surfaces of the polysiliconinterconnection 4 b and the interconnection protection film 15 b and astep sidewall 7 c are formed, the insulating film 12 with a thickness ofapproximately 0.15 μm is formed on the entire top surface.

Next, as is shown in FIG. 6(e), a resist film 25 d for forming aconnection hole is formed. At this point, in this embodiment, the resistfilm 25 d is formed so that the connection hole stretches over thepolysilicon electrode 4 a, the high-concentration source/drain region 8serving as the active area and the isolation 2 b when the mask alignmentshift is not caused in the lithography. Accordingly, when the alignmentshift is not caused, the exposing area of the resist film 25 d stretchesalso over a part of the polysilicon electrode 4 a. Then, the insulatingfilm 12 is patterned by dry etching. At this point, a part of theisolation 2 b and the gate protection film 15 a in the exposing area ofthe resist film 25 d are also removed by some amount by the over-etch inthe dry etching of the insulating film 12. However, the connection hole14 never reaches the polysilicon electrode 4 a.

Then, as is shown in FIG. 6(f), a polysilicon film is deposited on theentire top surface and then patterned, thereby forming a localinterconnection 13 to be connected with the high-concentrationsource/drain region 8.

In this embodiment, the problems of the degradation of the junctionvoltage resistance and the increase of the junction leakage current canbe avoided as in the aforementioned embodiments even when the insulatingfilm 12 is 40% over-etched than its thickness of 0.15 μm in order toform the connection hole 14.

In particular in this embodiment, the connection hole 14 stretches alsoover the polysilicon electrode 4 a when the alignment shift is notcaused in the lithography. Therefore, when the insulating film 12 is,for example, 40% over-etched than its thickness of 0.15 μm in the dryetching thereof, although a part of the gate protection film 15 a isetched by a thickness of approximately 0.06 μm. However, theconventional problem of the electric short circuit with aninterconnection on an upper layer through the connection hole can beavoided since the thickness of the gate protection film 15 a is 0.15 μm,which is sufficiently larger than 0.06 μm.

It is noted that the thickness of the gate protection film 15 a can bedetermined as follows: The dimensions and materials of the respectivecomponents are determined so as to satisfy the following inequality (2),wherein “a” denotes the thickness of the insulating film 12; “c” denotesthe thickness of the gate protection film 4 a, “ER1” denotes the etchingrate of the insulating film 12; “ER3” denotes the etching rate of thegate protection film 4 a; and “OE” denotes the over-etch ratio of theinsulating film 12 in the formation of the connection hole 14:OE×a×(ER 3/ER 1)<c   (2)

At this point, a distance Ld between the polysilicon electrode 4 aserving as the gate electrode and the isolation 2 b is estimated as anindex of the integration. The distance Ld is 0.7 μm, namely, the sum ofthe diameter of the connection hole, 0.5 μm, the width of the electrodesidewall 7 a, 0.1 μm, and the width of the step sidewall 7 c, 0.1 μm.Thus, the distance Ld can be decreased by 0.5 μm as compared with theconventional distance of 1.2 μm.

Embodiment 6

Embodiment 6 will now be described referring to FIGS. 7(a) through 7(c).In manufacturing procedures described in this embodiment, a connectionhole for connecting an interconnection layer and a silicon substrate isformed so as to stretch over an active area, an electrode sidewall andan isolation when the alignment shift is not caused, and is formed so asto stretch also over a polysilicon electrode only when the alignmentshift is caused.

FIG. 7(a) shows the state where the procedures described in Embodiment 5referring to FIGS. 6(a) through 6(d) have been completed. Specificallyin FIG. 7(a), after an isolation 2 b having a top surface higher in astepwise manner than the surface of the active area, a step sidewall 7 con the side surface of the step portion of the isolation 2 b, a gateoxide film 3, a polysilicon electrode 4 a serving as a gate electrode, agate protection film 15 a on the polysilicon electrode 4 a, electrodesidewalls 7 a on both side surfaces of the polysilicon electrode 4 a andthe gate protection film 15 a, a low-concentration source/drain region6, a high-concentration source/drain region 8, a polysiliconinterconnection 4 b on the isolation 2 b, an interconnection protectionfilm 15 b on the polysilicon interconnection 4 b, and interconnectionsidewalls 7 b on both side surfaces of the polysilicon interconnection 4b and the interconnection protection film 15 b are formed, an insulatingfilm 12 having a thickness of approximately 0.15 μm is formed on theentire top surface.

Next, as is shown in FIG. 7(b), a resist film 25 e having a pattern forforming a connection hole is formed. At this point, in this embodiment,the resist film 25 e is formed so that its exposing area can expose atleast the step sidewall 7 c and the high-concentration source/drainregion 8 serving as the active area and stretches also over theelectrode sidewall 7 a.

Then, a polysilicon film is deposited on the entire top surface andpatterned, thereby forming a local interconnection 13 to be connectedwith the high-concentration source/drain region 8 is In the procedureshown in FIG. 7(b) of this embodiment, when the exposing area of theresist film 25 e is shifted by, for example, a maximum of 0.3 μm due tothe alignment shift in the lithography, the connection hole 14 is formedso as to stretch also over a part of the polysilicon electrode 4 a. Whenthe exposing area of the resist film 25 e is shifted in the reversedirection, the connection hole 14 is formed so as to stretch also over apart of the isolation 2 b. However, in either case, the junction voltageat the edge of the isolation 2 b is prevented from degrading and thejunction leakage current is prevented from increasing as far as thedimensions and the like of the respective components are determined soas to satisfy the inequalities (1) and (2). In addition, an electricalshort circuit between an interconnection member such as the localinterconnection and the polysilicon electrode 4 a can be avoided.

At this point, a distance Le between the polysilicon electrode 4 aserving as the gate electrode and the isolation 2 b is estimated as anindex of the integration. Similarly to Embodiment 5, the distance Le is0.7 μm, namely, the sum of the diameter of the connection hole, 0.5 μm,the width of the electrode sidewall 7 a, 0.1 μm, and the width of thestep sidewall 7 c, 0.1 μm. Thus, the distance Le can be decreased by 0.5μm as compared with the conventional distance of 1.2 μm.

In each of the aforementioned embodiments, the local interconnection isadopted as the interconnection member so as to make the insulating film12 comparatively thin. However, each embodiment can be applied to aninterconnection member using a general global interconnection formedwith an interlayer insulating film sandwiched. When the globalinterconnection is adopted, the interlayer insulating film iscomparatively thick. Therefore, the effects of the embodiments can besimilarly attained by decreasing the over-etch ratio of the interlayerinsulating film in the formation of the connection hole or by increasingthe level difference between the top surface of the isolation and thesurface of the active area. This will be described in more detail inEmbodiment 7 below.

Furthermore, when the isolation 2 b and the gate protection film 15 aused in Embodiment 5 or 6 are made of a material having a smalleretching rate than the material for the insulating film 12 against theetching for forming the connection hole, the semiconductor device can bemanufactured with more ease.

In addition, when the insulating film 12 in each of the aforementionedembodiments has a multilayered structure including at least one lowerlayer made of a material having a smaller etching rate against theetching for forming the connection hole, the semiconductor device can bemanufactured with more ease.

Embodiment 7

Embodiment 7 will now be described in which an is interconnection layerformed on a thick interlayer insulating film is connected with an activearea of a semiconductor substrate through a contact hole formed on theinterlayer insulating film.

FIGS. 8(a) through 8(c) are sectional views for showing procedures forforming a layered film 10 and an interlayer insulating film 11 insteadof the comparatively thin insulating film 12 of Embodiment 1. As isshown in FIG. 8(a), after conducting the procedures shown in FIGS. 1(a)through 1(d) and 2(a) through 2(c), a layered film 10 including asilicon oxide film 10 a with a thickness of approximately 70 nm and asilicon nitride film 10 b with a thickness of approximately 80 nm isformed on the entire top surface of the substrate. Then, an interlayerinsulating film 11 of a silicon oxide film with a thickness ofapproximately 600 nm is deposited thereon. Next, a resist film 25 ahaving a pattern for forming a contact hole is formed on the interlayerinsulating film 11. At this point, the exposing area of the resist film25 a is positioned without an alignment margin for avoiding interferencewith an isolation 2 b. In FIG. 8(a), the resist film 25 a is formed sothat the exposing area stretches over a source/drain region 8 serving asthe active area of a transistor and the isolation 2 b.

Next, as is shown in FIG. 8(b), etching is conducted by using the resistfilm 25 a as a mask, thereby selectively removing the interlayerinsulating 25 a and the layered film 10. Thus, a contact hole 20stretching over the isolation 2 b and the active area is formed.

Then, as is shown in FIG. 8(c), a plug underlying film 21 made of aTiN/Ti film and a W plug 22 are deposited within the contact hole 20 byselective CVD. Furthermore, an aluminum alloy film is deposited on theentire top surface of the substrate and the aluminum alloy film ispatterned, thereby forming a first layer metallic interconnection 23. Atthis point, the first layer metallic interconnection 23 is electricallyconnected with the source/drain region 8 serving as the active areathrough the W plug 22 and the plug underlying film 23 filled in thecontact hole 20.

FIGS. 9(a) through 9(c) are sectional views for showing procedures forforming a layered film 10 and an interlayer insulating film 11 insteadof the comparatively thin insulating film 12 of Embodiment 2. In thesemanufacturing procedures, a procedure for forming sidewalls 7 a through7 c is added to the manufacturing procedures shown in FIGS. 8(a) through8(c), so as to manufacture a transistor having the LDD structure.

FIGS. 10(a) through 10(c) are sectional views for showing procedures forforming a layered film 10 and an interlayer insulating film 11 insteadof the comparatively thin insulating film 12 of Embodiment 4. In theprocedure shown in FIG. 10(a), a resist film 25 c having its exposingarea stretching over the active area and the gate interconnection 4 b isformed on the interlayer insulating film 11. Thereafter, the sameprocedures as those shown in FIGS. 8(b) and 8(c) are conducted.

FIGS. 11(a) through 11(c) are sectional views for showing procedures forforming a layered film 10 and an interlayer insulating film 11 insteadof the comparatively thin insulating film 12 of Embodiment 5. In theprocedure shown in FIG. 11(a), a gate protection silicon oxide film 15 ais formed on a gate electrode 4 a, and the layered film 10 and theinterlayer insulating film 11 are formed thereon. Then, a resist film 25d having its exposing area stretching over the isolation, the activearea and the gate electrode 4 a is formed on the interlayer insulatingfilm 11. Thereafter, the same procedures as those shown in FIGS. 8(b)and 8(c) are conducted.

In each of the procedures shown in FIGS. 8(b), 9(b), 10(b) and 11(b),the silicon nitride film 10 b having high etching selectivity againstthe silicon oxide film is formed below the interlayer insulating film11. Therefore, the silicon nitride film 10 b is prevented from beingcompletely removed by the over-etch in etching the interlayer insulatingfilm 11. When the silicon nitride film 10 b is to be removed from thelayered film 10, the silicon oxide film 10 a is prevented from beingcompletely removed since the etching selectivity between the siliconnitride film 10 b and the silicon oxide film 10 a below is high.Furthermore, since the silicon oxide film 10 a has a thickness ofapproximately 70 nm, which is smaller than the level difference of 0.2μm between the isolation and the active area, the isolation 2 b isprevented from being etched to be lower than the surface of the activearea by the over-etch in etching the silicon oxide film 10 a. In otherwords, a recess where the top surface of the isolation 2 b is lower thanthe surface of the silicon substrate is never formed in any part of thecontact hole 20. Accordingly, in the formation of the contact hole forelectrically connecting the interconnection layer formed on theinterlayer insulating film and the active area of the semiconductorsubstrate, the same effects as those described in the aforementionedembodiments can be attained.

However, the underlying film below the interlayer insulating film can beomitted in this embodiment. Even when it is omitted, since the stepportion is formed between the top surface of the isolation and thesurface of the active area, the isolation cannot be etched to be lowerthan the surface of the active area in the formation of the contacthole. Thus, the degradation of the junction voltage resistance theincrease of the junction leakage current can be prevented as much aspossible.

Embodiment 8

Embodiment 8 will now be described referring to FIGS. 12 and 13(a)through 13(e). FIG. 12 is a sectional view showing the structure of asemiconductor device of this embodiment, and FIGS. 13(a) through 13(e)are sectional views for showing manufacturing procedures for thesemiconductor device having the structure shown in FIG. 12.

As is shown in FIG. 12, in a silicon substrate (or well) 1 of oneconductivity type, a trench isolation 2 b is formed in an isolationregion Reiso for partitioning an area in the vicinity of the surface ofthe silicon substrate 1 into a plurality of transistor regions Refet.The top surface of the isolation 2 b is sufficiently higher than thesurface of the silicon substrate 1 in each transistor region Refet, anda step portion with a predetermined level difference is formed betweenthe isolation 2 b and the transistor region Refet. This isolation 2 b isformed by filling a trench formed in the silicon substrate 1 with aninsulating material as described below. Furthermore, a channel stopregion 60 of the same conductivity type as that of the silicon substrate1 is formed at least below the isolation 2 b.

In each transistor region Refet partitioned by the isolation 2 b isformed a MOS transistor including a gate electrode 4 a, a gate oxidefilm 3, electrode sidewalls 7 a, a low-concentration source/drain region6 and a high-concentration source/drain region 8. Also, on the siliconsubstrate 1 excluding the transistor regions Refet and on the isolation2 b, a gate interconnection 4 b formed simultaneously with the gateelectrode 4 a and interconnection sidewalls 7 b are formed. Furthermore,an upper gate electrode 9 a, an upper gate interconnection 9 b and asource/drain electrode 9 c each made of titanium silicide (TiSi₂) areformed on the gate electrode 4 a, the gate interconnection 4 b and thehigh-concentration source/drain region 8, respectively.

This embodiment is characterized by a step sidewall 7 c formed on theside surface of the step portion of the isolation 2 b simultaneouslywith the electrode sidewalls 7 a and the interconnection sidewalls 7 b.A part of the step sidewall 7 c is communicated with the electrodesidewalls 7 a and the interconnection sidewalls 7 b.

Furthermore, on the entire top surface of the substrate bearing theisolation 2 b, the gate electrode 4 a and the like, an interlayerinsulating film 11 and a first layer metallic interconnection 23 areformed. The first layer metallic interconnection 23 is connected withthe upper gate electrode 9 a and the source/drain electrode 9 c in thetransistor region through a W plug 22.

Now, the manufacturing procedures for realizing the structure shown inFIG. 12 will be described referring to FIGS. 13(a) through 13(e).

First, as is shown in FIG. 13(a), a silicon oxide film 52 and a siliconnitride film 53 are deposited on a silicon substrate 1. Then, a resistfilm 50 a for exposing the isolation regions Reiso and masking thetransistor regions Refet is formed on the silicon nitride film 53. Afterthis, etching is conducted by using the resist film 50 a as a mask, soas to selectively remove the silicon nitride film 53 and the siliconoxide film 52 and further etch the silicon substrate 1, thereby forminga trench 51. At this point, differently from the conventional method offorming a trench, the silicon nitride film 53 has a thickness as largeas approximately 150 through 200 nm. However, the silicon oxide film 52has a thickness of 10 through 20 nm as in the conventional method. Thedepth of the trench 51 can be approximately 500 nm also as in theconventional method. Then, impurity ions of a conductivity typedifferent from that of an impurity to be injected into a subsequentlyformed source/drain region are injected, thereby forming a channel stopregion 60.

Next, as is shown in FIG. 13(b), after removing the resist film 50 a, asilicon oxide film (not shown) is deposited so as to have a sufficientthickness larger than the sum of the depth of the trench 51 and thethickness of the remaining silicon nitride film 53, namely, the heightfrom the bottom of the trench 51 to the top surface of the siliconnitride film 53. Then, the silicon oxide film is removed by the CMPmethod so as to expose the surface of the silicon nitride film 53,thereby flattening the entire top surface of the substrate. Through thisprocedure, a trench isolation 2 b made of the silicon oxide film isformed in the isolation region Reiso. The flattening method to beadopted is not limited to that described above but the surface can beflattened by etch-back using a resist film having a reverse pattern tothe pattern of the transistor region Refet.

Then, the silicon nitride film 53 is removed by using a phosphoric acidboiling solution or the like and the silicon oxide film 52 is removed byusing a hydrofluoric acid type wet etching solution or the like, so asto expose the surface of the silicon substrate 1 in the transistorregion Refet, which procedures are not shown in the drawing. At thispoint, a step portion having a sufficient level difference between thesurface of the silicon substrate 1 in the transistor region Refet andthe top surface of the isolation 2 b is exposed characteristically inthis embodiment. The level difference is set at approximately 50 through100 nm in consideration of the amount of over-etch in a procedure forforming sidewalls described below. However, in order to effectivelyachieve the effects of this embodiment, the thickness of an insulatingfilm for the sidewall and the amount of over-etch are required to beappropriately determined in the subsequent procedure for forming thesidewalls.

Then, as is shown in FIG. 13(c), a polysilicon film 4 is deposited onthe silicon substrate 1 and the isolation 2 b, and the resist film 50 bfor exposing an area excluding the areas for a gate electrode and a gateinterconnection is formed thereon. Then, the dry etching is conducted byusing the resist film 50 b as a mask, thereby forming the gate electrode4 a and the gate interconnection 4 b, which procedure is not shown inthe drawing.

Next, as is shown in FIG. 13(d), by using the gate electrode 4 a as amask, impurity ions at a low concentration are injected, thereby forminga low-concentration source/drain region 6. Then, an insulating film 7 (asilicon oxide film) is deposited on the entire top surface of thesubstrate.

Then, as is shown in FIG. 13(e), the insulating film 7 isanisotropically etched, thereby forming the electrode sidewalls 7 a onthe both side surfaces of the gate electrode 4 a and interconnectionsidewalls 7 b on the both side surfaces of the gate interconnection 4 b.At the same time, a step sidewall 7 c is formed on the side surface ofthe step portion between the silicon substrate 1 in the transistorregion Refet and the isolation 2 b. After forming these sidewalls,impurity ions are injected, thereby forming the high-concentrationsource/drain region 8. Also at this point, the step portion between thesilicon substrate 1 in the transistor region Refet and the isolation 2 bhas the sufficient level difference.

Although the procedures thereafter are not shown in the drawing, anupper gate electrode 9 a, an upper gate interconnection 9 b and asource/drain electrode 9 c are formed by a silicifying procedure, aninterlayer insulating film 11 is deposited and a contact hole is formed,and then the contact hole is filled with a metal, and a first layermetallic interconnection 12 is formed. In this manner, the MOStransistor having the trench isolation structure as shown in FIG. 12 ismanufactured.

In the aforementioned procedures, the electrode sidewalls 7 a and thelike are formed in order to manufacture a transistor with the LDDstructure. However, the electrode sidewalls 7 a and the like can beformed in a transistor having the so-called pocket injection structure,in which a punch-through stopper is formed by injecting an impurity of adifferent conductivity type into an area between the source/drain regionand the channel region. Therefore, this embodiment is applicable to sucha transistor having the pocket injection structure.

In manufacturing a MOS transistor having a gate length of 1 μm or lessas in this embodiment, it is necessary to form the electrode sidewalls 7a on the side surfaces of the gate electrode 4 a in order to provide thetransistor with the LDD structure or the pocket injection structure inwhich the short channel effect can be suppressed and the reliability ofthe transistor can be ensured. The thickness of the electrode sidewall 7a depends upon the characteristics of a device to be manufactured. Sincethe sidewall is formed by dry etching with high anisotropy, itsthickness can be controlled substantially only by controlling thethickness of the film to be deposited. However, 10% through 30%over-etch is generally conducted in consideration of the fluctuation inthe etching rate in the wafer and the fluctuation in the thickness ofthe deposited film. For example, when the electrode sidewall 7 a isformed out of an insulating film with a thickness of 100 nm, the etchingis conducted for a time period corresponding to time required forremoving an insulating film with a thickness of 110 through 130 nm.

At this point, the isolation 2 b made of an oxide film is etched athigher selectivity than the silicon substrate 1 in the transistor regionRefet, and hence, the isolation 2 b is removed by a thickness of, forexample, 10 through 30 nm. Therefore, in the conventional structure, thesurface of the isolation 105 a becomes lower than the surface of thesilicon substrate 101 as is shown in FIGS. 21(a) and 21(b), resulting incausing the aforementioned problems. In contrast, in the state of thisembodiment shown in FIG. 13(d), the isolation 2 b has the step portionwhose surface is higher than the surface of the silicon substrate in thetransistor region Refet, resulting in effectively preventing theproblems. In other words, even when the impurity ions are diagonallyinjected for the formation of the high-concentration source/drain region8, the impurity ions are prevented from being implanted below the edgeof the isolation 2 b because the step portion of the isolation 2 b has asufficient level difference. Accordingly, a distance between thehigh-concentration source/drain region 8 and the channel stop region 60can be made substantially constant, thereby preventing the degradationof the junction voltage resistance and the increase of the junctionleakage. Furthermore, in the formation of the source/drain electrode 9 cof silicide on the high-concentration source/drain region 8, the stepsidewall 7 c effectively prevents the silicide layer from being formedin the boundary between the silicon substrate 1 and the isolation 2 b.Therefore, it is possible to effectively prevent a short circuit currentfrom occurring between the source/drain electrode 9 c and the channelstop region 60.

In order to effectively achieve the aforementioned effects in thisembodiment, however, the level difference caused by the step portion ispreferably larger than the amount of over-etch in the formation of thesidewalls, that is, 10 through 30 nm. Furthermore, in practical use,after the formation of the isolation 2 b, other procedures are conductedin which the thickness of the silicon oxide film used as the isolation 2b is decreased, such as a procedure for removing the silicon oxide film52. Therefore, it is preferred that the step portion is previouslyformed so as to have a sufficiently large level difference also inconsideration of the afterward decreased amount. Accordingly, the lowerlimit of the thickness of the S silicon nitride film 53 deposited in theprocedure shown in FIG. 13(a) is determined on the basis of the amountof over-etch and the etched amount in the procedure for removing thesilicon oxide film 52.

In this embodiment, the silicon nitride film 53 is used as an etchingmask for forming the trench 51. This film can be made of any materialwhich has large etching selectivity against the silicon oxide film, andcan be, for example, a polysilicon film or the like.

This embodiment exemplifies the so-called salicide structure in whichthe upper gate electrode 9 a and the source/drain electrode 9 c aresimultaneously silicified in a self-aligned manner for attaining lowresistance. It goes without saying that the embodiment is applicable toa structure in which a gate electrode is previously formed as a polycideelectrode and a source/drain electrode alone is silicified afterward.

Embodiment 9

Embodiment 9 will now be described referring to FIGS. 14(a) through14(e). This embodiment is different from Embodiment 8 in that a gateoxide film and a polysilicon film serving as a gate electrode aredeposited before forming a trench isolation.

First, as is shown in FIG. 14(a), a gate oxide film 3 and a polysiliconfilm 4 serving as a gate electrode of a MOS transistor are successivelydeposited on a silicon substrate 1. A resist film 50 a for exposing anisolation region Reiso and masking a transistor region Refet ispatterned. By using the resist film 50 a as a mask, the polysilicon film4 and the gate oxide film 3 are selectively removed, and further thesilicon substrate 1 is etched, thereby forming a trench 51 serving asthe isolation region. At this point, differently from the conventionalmethod of forming a trench, the thickness of the polysilicon film 4 isset at 150 through 200 nm, that is, substantially the same thickness asthat of the silicon nitride film used in Embodiment 8. The gate oxidefilm 3 has a thickness of 10 through 20 nm. The depth of the trench 51is approximately 500 nm. Then, impurity ions of a different conductivitytype from that of an impurity to be injected into a source/drain regionformed afterward are injected, thereby forming a channel stop region 60.

Then, after removing the resist film 50 a, a silicon oxide film 2 (notshown) is deposited so as to have a sufficient thickness larger than thesum of the depth of the trench 51 and the thickness of the remainingpolysilicon film 4, namely, the height from the bottom of the trench 51to the top surface of the polysilicon film 4. The silicon oxide film 2is removed by the CMP method until the surface of the polysilicon film 4is exposed, thereby flattening the top surface of the substrate. Throughthis procedure, a trench isolation 2 b made of the silicon oxide film isformed in the isolation region Reiso. The flattening method to beadopted is not limited to that described above but the surface can beflattened by etch-back using a resist film having a reverse pattern tothe pattern of the transistor region Refet.

Next, as is shown in FIG. 14(b), a conductive film 18 serving as a gateinterconnection layer (which can be made of a conductive polysiliconfilm; a silicide film of WSi, TiSi or the like; or a metal with a highmelting point such as W with a sandwiched barrier metal such as TiN forachieving low resistance) and a protection film 19 made of an insulatingfilm are deposited on the flattened substrate. Then, a resist film 50 bfor exposing an area excluding the areas for a gate electrode and a gateinterconnection is formed. By using the resist film 50 b as a mask, dryetching is conducted, thereby forming a gate electrode 4 a, an uppergate electrode 18 a and a protection film 19 a, a gate interconnection 4b, an upper gate interconnection 18 b and a protection film 19 b, whichprocedures are not shown in the drawing. At this point, a step portionhaving a sufficient level difference between the surfaces of the siliconsubstrate 1 in the transistor region Refet and the isolation 2 b isexposed characteristically in this embodiment. The level difference isapproximately 50 through 100 nm in consideration of the amount ofover-etch in the subsequent procedure for forming sidewalls and thelike. However, in order to effectively achieve the effects of thisembodiment, the thickness of an insulating film for the sidewall and theamount of over-etch are required to be appropriately determined in thesubsequent procedure for forming the sidewalls.

Then, as is shown in FIG. 14(c), similarly to Embodiment 8, afterforming a low-concentration source/drain region 6 on either side of thegate electrode 4 a in the active area, an insulating film 7 (siliconoxide film) is deposited on the entire top surface of the substrate.

Next, as is shown in FIG. 14(d), the insulating film 7 isanisotropically etched, thereby forming electrode sidewalls 7 a on bothside surfaces of the gate electrode 4 a and the like and interconnectionsidewalls 7 b on both side surfaces of the gate interconnection 4 b andthe like. At the same time, a step sidewall 7 c is formed on the sidesurface of the step portion between the silicon substrate 1 in thetransistor region Refet and the isolation 2 b. After forming thesesidewalls, impurity ions are injected, thereby forming ahigh-concentration source/drain region 8. Also at this point, the stepportion between the silicon substrate 1 in the transistor region Refetand the isolation 2 b has a sufficient level difference.

Next, as is shown in FIG. 14(e), a source/drain electrode 9 c is formedout of silicide only on the high-concentration source/drain region 8.

Although the procedures thereafter are not shown in the drawing, aninterlayer insulating film 11 is deposited, a contact hole is formed,and the contact hole is filled with a metal (such as tungsten), and afirst layer metallic interconnection 12 is formed. Thus, a MOStransistor having a trench isolation similar to that shown in FIG. 12 ismanufactured. In this embodiment, however, on the gate electrode 4 a andthe gate interconnection 4 b are formed the upper gate electrode 18 aand the upper gate interconnection 18 b made of conductive polysilicon,silicide or the like as well as the protection films 19 a and 19 b madeof the insulating film, respectively. The source/drain electrode 9 c ofsilicide is formed in the procedure different from that for forming theupper gate electrode 18 a and the upper gate interconnection 18 b.

In this manner, the step portion which is higher at the side closer tothe isolation 2 b is formed between the silicon substrate 1 in thetransistor region Refet and the isolation 2 b, and the step portion isprovided with the step sidewall 7 c on its side surface in thisembodiment. Therefore, the same effects as those of Embodiment 8 can beexhibited with a reduced number of manufacturing procedures.

In addition, the procedure for forming the gate electrode 4 a and thegate interconnection 4 b after the procedure shown in FIG. 14(b) can beconducted on the completely flat top surface of the substrate withoutbeing affected by the step portion at the edge of the isolation 2 b inthis embodiment. Therefore, a refined pattern can be advantageouslystably formed.

Embodiment 10

Embodiment 10 will now be described referring to FIGS. 15(a) through15(f), which are sectional views for showing manufacturing proceduresfor a semiconductor device of this embodiment.

Before achieving the state shown in FIG. 15(a), a trench isolation 2 b,a channel stop region 60, a low-concentration source/drain region 6, agate insulating film 3, a gate electrode 4 a, a gate interconnection 4 band the like are formed through the same procedures as those describedin Embodiment 8. Then, a protection oxide film 31, a silicon nitridefilm 32 for sidewalls and a polysilicon film 33 for a mask are depositedon the substrate by the CVD method. At this point, the thickness of apolysilicon film to be used as the gate electrode 4 a and the gateinterconnection 4 b is 330 nm, and the minimum line width is 0.35 μm.The protection oxide film 31 has a thickness of approximately 20 nm, thesilicon nitride film 32 has a thickness of approximately 30 nm, and thepolysilicon film 33 has a thickness of approximately 100 nm.

Then, as is shown in FIG. 15(b), the polysilicon film 33 is etched backby RIE (reactive ion etching), thereby forming electrode polysiliconmasks 33 a, interconnection polysilicon masks 33 b and a steppolysilicon mask 33 c on side surfaces of the gate electrode 4 a, thegate interconnection 4 b and a step portion of the isolation 2 b,respectively. At this point, the etching selectivity between thepolysilicon film 33 and the silicon nitride film 32 is large.

Next, as is shown in FIG. 15(c), by using the remaining polysiliconmasks 33 a, 33 b and 33 c as masks, wet etching using heated phosphoricacid (H₃PO₄) at 150° C. is conducted, so as to have portions of thesilicon nitride film 32 covered with the polysilicon masks 33 a, 33 band 33 c remained and remove the other portions thereof. At this point,the etching selectivity between the silicon nitride film 32 and thepolysilicon masks 33 a, 33 b and 33 c can be approximately 30:1. Throughthis procedure, electrode sidewalls 32 a, interconnection sidewalls 32 band a step sidewall 32 c each having an L-shape remain on the sides ofthe gate electrode 4 a, the gate interconnection 4 b and the stepportion, respectively.

Then, as is shown in FIG. 15(d), by using the gate electrode 4 a, theprotection oxide film 31, the electrode polysilicon mask 33 a, theelectrode sidewall 32 a, the step polysilicon mask 33 c and the stepsidewall 32 c as masks, impurity ions are injected at a highconcentration into the active area of the silicon substrate 1, therebyforming a high-concentration source/drain region 8.

Then, as is shown in FIG. 15(e), the polysilicon masks 33 a, 33 b and 33c are removed by dry or wet etching.

Next, as is shown in FIG. 15(f), exposed portions of the protectionoxide film 31 on the substrate are removed by using a HF type etchingsolution. Then, a titanium film is deposited and a first RTA treatmentis conducted, thereby forming a silicide layer of a TiSi₂ film throughthe reaction between titanium and silicon. The titanium film is thenremoved, and a second RTA treatment is conducted, so that an upperelectrode 9 a, an upper interconnection 9 b and a source/drain electrode9 c each of a silicide layer with a low resistance are formed on thegate electrode 4 a, the gate interconnection 4 b and the source/drainregion 8, respectively. Thereafter, an interlayer insulating film isdeposited, the top surface of the substrate is flattened, a contact holeis formed, a metallic interconnection film is deposited, and a metallicinterconnection is formed. Thus, an LSI is manufactured.

Since the protection oxide film 31 and the L-shaped step sidewall 32 care formed on the side surface of the step portion in the procedureshown in FIG. 15(f) in this embodiment, the silicide layer iseffectively prevented from being formed in the boundary between theactive area of the silicon substrate 1 and the isolation 2 b.

Furthermore, since the protection oxide film 31 is formed on theisolation 2 b and the active area of the silicon substrate 1 in theprocedures shown in FIGS. 15(c) and 15(d), the thickness of theisolation 2 b is never decreased through the formation of the L-shapedsidewalls 32 a, 32 b and 32 c. Accordingly, it is possible to decreasethe level difference between the isolation 2 b and the silicon substrate1, resulting in improving the patterning accuracy for the gate.

In the formation of the gate electrode, first and second conductivefilms can be used similarly to Embodiment 2. Also in this case, the sameeffects as those of this embodiment can be exhibited.

Embodiment 11

In each of the aforementioned embodiments, each sidewall is made of aninsulating material such as a silicon oxide film and a silicon nitridefilm. The sidewall can be made of a conductive material such as apolysilicon film. FIG. 16(a) through 16(e) are sectional views forshowing manufacturing procedures for a semiconductor device includingconductive sidewalls.

Before attaining the state shown in FIG. 16(a), a trench is isolation 2b, a channel stop region 60, a low-concentration source/drain region 6,a gate insulating film 3, a gate electrode 4 a, a gate interconnection 4b and the like are formed through the same procedures as those describedin Embodiment 8. Then, a protection oxide film 31 and a polysilicon film34 for sidewalls are deposited on the top surface by the CVD method. Inthis embodiment, on the gate electrode 4 a and the gate interconnection4 b are formed protection silicon oxide films 15 a and 15 b,respectively. At this point, a polysilicon film to be used as the gateelectrode 4 a and the gate interconnection 4 b has a thickness of 330nm, and the minimum line width is 0.35 μm. The protection oxide film 31has a thickness of approximately 20 nm and the polysilicon film 34 has athickness of approximately 100 nm.

Next, as is shown in FIG. 16(b), the polysilicon film 34 is etched backby the RIE, thereby forming electrode sidewalls 34 a, interconnectionsidewalls 34 b and a step sidewall 34 c each made of the polysiliconfilm on sides of the gate electrode 4 a, the gate interconnection 4 band a step portion of the isolation 2 b, respectively.

Next, as is shown in FIG. 16(c), by using the gate electrode 4 a, theprotection oxide film 31, the electrode sidewalls 34 a and the stepsidewall 34 c as masks, impurity ions are injected at a highconcentration into an active area of the silicon substrate 1, therebyforming a high-concentration source/drain region 8.

Then, as is shown in FIG. 16(d), exposed portions of the protectionoxide film 31 on the substrate are removed by using the HF type etchingsolution. Then, as is shown in FIG. 16(e), a titanium film is depositedand a first RTA treatment is conducted, thereby forming a silicide layermade of a TiSi₂ film through the reaction between titanium and silicon.The titanium film is then removed and a second RTA treatment isconducted, thereby forming a source/drain electrode 9 d made of asilicide layer stretching over the electrode sidewall 34 a, thehigh-concentration source/drain region 8 and the step sidewall 34 c.Since the silicide layer is formed also on the interconnection sidewall34 b, this silicide layer can be connected with the source/drainelectrode. Therefore, in this embodiment, etching is conducted on theisolation 2 b by using a resist film or the like, so as to selectivelyremove the interconnection sidewalls 34 b on the sides of the gateinterconnection 4 b as well as the silicide layer thereon. Thus, thesource/drain electrodes 9 d in the respective active areas are preventedfrom being mutually connected. It is possible to selectively removemerely the interconnection sidewalls 34 b on the sides of the gateinterconnection 4 b immediately after forming the sidewalls 34 a, 34 band 34 c of the polysilicon film.

Thereafter, an interlayer insulating film is deposited, the top surfaceof the substrate is flattened, a contact hole is formed, a metallicinterconnection film is deposited, and a metallic interconnection isformed. Thus, an LSI is manufactured.

In this embodiment, the source/drain electrode 9 d is ultimately formedso as to stretch over a large area including the electrode sidewall 34a, the high-concentration source/drain region 8 and the step sidewall 34c. Accordingly, the level difference between the transistor region Refetand the isolation 2 b can effectively prevent the high-concentrationsource/drain region 8 from being brought close to the channel stopregion 60 in the impurity ion injection. Furthermore, in the formationof the source/drain electrode 9 d of silicide on the high concentrationsource/drain region 8, also the step sidewall 34 c is silicified by acertain thickness. However, since the silicide layer is prevented frombeing formed in a further thickness, a short circuit current between thesource/drain electrode 9 d and the channel stop region 60 is effectivelyprevented from being caused by the formation of the silicide layer inthe interface between the isolation and the silicon substrate. Moreover,since the large area stretching over the electrode sidewall 34 a, thehigh-concentration source/drain region 8 and the step sidewall 34 c issilicified in this embodiment, it is very easy to form a contact memberto be connected with an upper first layer interconnection. As a result,the area of the transistor region Refet can be decreased, namely, theintegration of the semiconductor device can be advantageously improved.Although the electrode sidewalls 34 a and the interconnection sidewalls34 b are made of a conductive polysilicon film, there is no possibilityof a short circuit between the sidewall and the gate because therespective sidewalls 34 a and 34 b are insulated from the gate electrode4 a and the gate interconnection 4 b by the protection oxide film 31.

In the formation of the gate electrode, first and second conductivefilms can be used similarly to Embodiment 9, and also in this case, thesame effects as those of this embodiment can be attained.

The sidewalls are made of a polysilicon film in this embodiment, and thepolysilicon film can be replaced with an amorphous silicon film.Furthermore, the sidewalls can be made not only of a silicon film butalso of another conductive material such as a metal, and it is notnecessarily required to silicify the sidewalls.

In each of the aforementioned embodiments, the description is made onthe case where the semiconductor element formed in the active area is afield effect transistor. However, the invention is not limited to theseembodiments, and is applicable when the semiconductor element is abipolar transistor and the active area is an emitter diffused layer, acollector diffused layer or a base diffused layer of the bipolartransistor.

In each embodiment, setting of an angle of the side surface of the stepportion to be equal to or more than 70° ensures a large level differencebetween the active area and the side surface of the step portion aroundthe boundary of the active area, thereby preventing formation of a deeprecess on the isolation.

1-38. (canceled)
 39. A semiconductor device, comprising: an isolationinsulating area surrounding an active area of a semiconductor substrate;a gate insulating film formed over the active area; a gate electrodeformed over the gate insulating film; first L-shaped sidewalls formedover the side surfaces of the gate electrode; and first silicide layersformed on regions located on the sides of the first L-shaped sidewallswithin the active area.
 40. The semiconductor device of claim 39,wherein the first L-shaped sidewalls are made of a silicon nitride film.41. The semiconductor device of claim 39, further comprising firstprotection oxide films formed between the gate electrode and the firstL-shaped sidewalls.
 42. The semiconductor device of claim 39, furthercomprising a second silicide layer formed on the gate electrode.
 43. Thesemiconductor device of claim 39, further comprising source/drainregions formed on both sides of the gate electrode within the activearea, wherein the first silicide layers are formed on the source/drainregions.
 44. The semiconductor device of claim 39, further comprising aninterconnection formed over the isolation insulating area; and secondL-shaped sidewalls formed over the side surfaces of the interconnection.45. The semiconductor device of claim 44, the second L-shaped sidewallsare made of a silicon nitride film.
 46. The semiconductor device ofclaim 44, further comprising second protection oxide films formedbetween the interconnection and the second L-shaped sidewalls.
 47. Thesemiconductor device of claim 44, further comprising a third silicidelayer formed on the interconnection.
 48. The semiconductor device ofclaim 39, wherein the isolation insulating area is a trench isolation.49. The semiconductor device of claim 48, wherein the trench isolationhas an upper surface higher than the surface of the active area.
 50. Thesemiconductor device of claim 48, wherein a lower portion of theinterconnection provided on the upper surface of the trench isolation islocated higher than the surface of the active area.
 51. Thesemiconductor device of claim 44, wherein the interconnection iscomposed of the same material as the gate electrode.
 52. Thesemiconductor device of claim 51, wherein the gate electrode and theinterconnection has at least a polysilicon film.